The present invention relates to semiconductor based memory devices, and in particular to controlling timing in a dynamic random access memory (DRAM) based on row repair.
Semiconductor memory devices are becoming more and more complex as their size decreases and their storage density increases. To help handle some of the increase in storage density, an architecture comprising multiple subarrays of memory cells on a die for storing values such as bits has been adopted in dynamic random access memory (DRAM) devices. Each of the subarrays comprises multiple rows of memory cells that are accessed or xe2x80x9cfiredxe2x80x9d by activation of row address signals. Occasionally, during manufacture, one or more rows is defective. Some of these rows may be replaced via a fuse option with redundant rows such as shown in U.S. Pat. No. 5,528,539 to Ong et. al. When a redundant row is used, the DRAM""s internal timing needs to be slightly slowed down, to provide extra time for address compare and override to the redundant rows. Repair of DRAMs during manufacturing happens on a manageably small percentage of parts, often less than 50%. Therefore, it is not desirable to slow down every die regardless of row repair. In fact, it is desired to obtain faster row access speeds if possible.
Prior solutions have included providing circuits on the die that poll every redundant row bank on the die. If any are enabled, the RAS chain is slowed down. Such schemes, while easy to implement on smaller generation DRAMs, mandate a large number of line spaces and gates for the polling operation on higher density generation DRAMS, since there may be 16 to 64 row banks or more that are checked. This consumes valuable die space and adversely impacts efforts to further increase DRAM density.
There is a need for slowing down the RAS chain when redundant rows are used. There is a further need to only slow down the RAS chain when such redundant rows are in use. There is a need to slow down the RAS chain without using significant additional circuitry. In fact, it would be beneficial to reduce the amount of circuitry currently used to determine that the RAS chain needs to be slowed down.
A fuse option is provided in a memory device to selectively slow row address signals when redundant rows of memory cells have been selected for use. The fuse option is blown when a redundant row is used to replace a defective row as identified during manufacture of a chip. Use of the fuse allows removal of multiple lines and gates used to poll row banks to determine if a redundant row was in use. The removal of such lines and gates creates more room for other circuitry, contributing to the ability to create higher density memory devices.
In one embodiment, a fuse is coupled to delay circuitry which has a known delay. When the fuse is blown after detecting a defective row, the delay circuitry is coupled in series with selected portions of a row address strobe (RAS) chain of circuitry used to propagate row address selection signals to the proper rows. This provides extra time needed for row address compare and override circuitry, which is not in series with the delay circuitry.
In a further embodiment, an antifuse takes the place of the fuse and is coupled such that when it is set, the delay circuitry is appropriately coupled into the path of selected portions of the RAS chain. The present invention is usefully in the design and manufacture of dynamic random access memory (DRAM) devices.